MOS Technology 6502
Architecture
The 6502 has only three general-purpose registers: A, X, and Y, all of which are 8 bits wide. It also has an eight-bit stack pointer (S) and an eight-bit status register (P). The stack is hardwired to page 1 (\$0100–\$01FF) and grows down. Addresses are always stored in little-endian format.
Instruction set
6502 instructions can often use multiple addressing modes. Examples include:
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implied: TAX
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immediate: ADC #\$01
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zero page: STX \$A3
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zero page indexed: LDX \$3A,Y
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absolute: LDA \$2000
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indirect: JMP (\$C1FF)
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relative: BEQ -5
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absolute indexed: EOR \$2000,X / AND \$2000,Y
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indexed indirect: CMP (\$65,X)
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indirect indexed: ORA (\$55),Y
Out of a possible 256, the NMOS 6502 had only 151 legal opcodes. Because the chip used a PLA instruction decoder, the illegal opcodes could have effects from combining existing valid instructions to completely locking up the processor [1].
Table 1: NMOS opcodes (illegal opcodes omitted) [2]
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x | BRK | ORA (a8,X) | ORA a8 | ASL a8 | PHP | ORA #d8 | ASL A | ORA a16 | ASL a16 | |||||||
| 1x | BPL r8 | ORA (a8),Y | ORA a8,X | ASL a8,X | CLC | ORA a16,Y | ORA a16,X | ASL a16,X | ||||||||
| 2x | JSR a16 | AND (a8,X) | BIT a8 | AND a8 | ROL a8 | PLP | AND #d8 | ROL A | BIT a16 | AND a16 | ROL a16 | |||||
| 3x | BMI r8 | AND (a8),Y | AND a8,X | ROL a8,X | SEC | AND a16,Y | AND a16,X | ROL a16,X | ||||||||
| 4x | RTI | EOR (a8,X) | EOR a8 | LSR a8 | PHA | EOR #d8 | LSR A | JMP a16 | EOR a16 | LSR a16 | ||||||
| 5x | BVC r8 | EOR (a8),Y | EOR a8,X | LSR a8,X | CLI | EOR a16,Y | EOR a16,X | LSR a16,X | ||||||||
| 6x | RTS | ADC (a8,X) | ADC a8 | ROR a8 | PLA | ADC #d8 | ROR A | JMP (a16) | ADC a16 | ROR a16 | ||||||
| 7x | BVS r8 | ADC (a8),Y | ADC a8,X | ROR a8,X | SEI | ADC a16,Y | ADC a16,X | ROR a16,X | ||||||||
| 8x | STA (a8,X) | STY a8 | STA a8 | STX a8 | DEY | TXA | STY a16 | STA a16 | STX a16 | |||||||
| 9x | BCC r8 | STA (a8),Y | STY a8,X | STA a8,X | STX a8,Y | TYA | STA a16,Y | TXS | STA a16,X | |||||||
| Ax | LDY #d8 | LDA (a8,X) | LDX #d8 | LDY a8 | LDA a8 | LDX a8 | TAY | LDA #d8 | TAX | LDY a16 | LDA a16 | LDX a16 | ||||
| Bx | BCS r8 | LDA (a8),Y | LDY a8,X | LDA a8,X | LDX a8,Y | CLV | LDA a16,Y | TSX | LDY a16,X | LDA a16,X | LDX a16,Y | |||||
| Cx | CPY #d8 | CMP (a8,X) | CPY a8 | CMP a8 | DEC a8 | INY | CMP #d8 | DEX | CPY a16 | CMP a16 | DEC a16 | |||||
| Dx | BNE r8 | CMP (a8),Y | CMP a8,X | DEC a8,X | CLD | CMP a16,y | CMP a16,X | DEC a16,X | ||||||||
| Ex | CPX #d8 | SBC (a8,X) | CPX a8 | SBC a8 | INC a8 | INX | SBC #d8 | NOP | CPX a16 | SBC a16 | INC a16 | |||||
| Fx | BEQ r8 | SBC (a8),Y | SBC a8,X | INC a8,X | SED | SBC a16,Y | SBC a16,X | INC a16,X |
Table 2: CMOS opcodes